1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a test item for a semiconductor memory device.
2. Description of the Related Art
In general, semiconductor memory devices, such as a Dynamic Random Access Memory (DRAM) device, support diverse test items. Diverse tests are performed to reduce the production costs of a semiconductor memory device and improve yield. Among such tests is a parallel test, which allows for a shorter test time.
Hereafter, the background of the parallel test is examined. It is important to test thousands of memory cells at a high speed as well as testing the semiconductor memory device with high reliability. Particularly, since the shortening of the test time until the shipment of products as well as shortening the time for developing a semiconductor memory device directly affect the production cost of the product, shortening the test time is a significant issue in terms of production efficiency and competition between manufacturers. The conventional semiconductor memory devices are tested for each memory cell to examine whether the memory cell has a failure or not. As a semiconductor memory device is highly integrated, the test time is increased in proportion to the integration degree. To reduce the time taken for the failure test, a parallel test is introduced. The process of the parallel test is performed as follows.
Briefly, in the parallel test, the same data are written in a plurality of cells. Then, when the same data are read from the cells using an exclusive OR gate, ‘1’ is outputted and a pass decision is made for the cells. When a different data is read from any one of the cells, ‘0’ is outputted and a failure decision is made. This parallel test is not performed for each memory cell, but performed by activating many banks at the same time and performing write and read operations. Therefore, the parallel test may shorten the test time.
Meanwhile, Double Data Rate 3 (DDR3) Dynamic Random Access Memory (DRAM) devices support a parallel test of an X4 mode and an X8 mode. The X4 mode performs a parallel test by using 4 pads, while the X8 mode performs a parallel test by using 8 pads.
Hereafter, a parallel test of the X4 mode is taken as an example and described.
First, a read path of a conventional semiconductor memory device is described with reference to FIG. 1.
FIG. 1 is a block diagram illustrating a read path of a conventional semiconductor memory device.
Referring to FIG. 1, the read path of the conventional semiconductor memory device includes first to eighth banks 111, 112, 113, 114, 115, 116, 117 and 118, each including a memory cell array of a plurality of memory cells; first to eighth compression blocks 121, 122, 123, 124, 125, 126, 127 and 128, which compress first to eighth bank data TGIO#<0:127> outputted from the first to eighth banks 111 to 118, respectively, and output first to eighth compressed data GIO_OT#<0:7> individually; and a read circuit 130 for outputting first to fourth read data DATA_DRV<0:3> to first to fourth pads DQ0, DQ1, DQ2 and DQ3, respectively, in response to the first to eighth compressed data GIO_OT#<0:7> and a read enable signal DR_EN. Herein, the first to eighth bank data TGIO#<0:127> are transferred through a first global input/output line disposed in a core region, and the first to eighth compressed data GIO_OT#<0:7> outputted from each compression block are transferred through a second global input/output line disposed in a peripheral region.
Meanwhile, the read circuit 130 includes first to fourth pipe latches 131A, 133A, 135A and 137A and first to fourth output circuits 131B, 133B, 135B and 137B. The first pipe latch 131A serializes a plurality of first compressed data GIO_OT0<0:7> or a plurality of second compressed data GIO_OT1<0:7> outputted from any one between the first compression block 121 and the second compression block 122 to output a first serial data DOUT<0>. The second pipe latch 133A serializes a plurality of third compressed data GIO_OT2<0:7> or a plurality of fourth compressed data GIO_OT3<0:7> outputted from any one between the third compression block 123 and the fourth compression block 124 to to output a second serial data DOUT<1>. The third pipe latch 135A serializes a plurality of fifth compressed data GIO_OT4<0:7> or a plurality of sixth compressed data GIO_OT5<0:7> outputted from any one between the fifth compression block 125 and the sixth compression block 126 to output a third serial data DOUT<2>. The fourth pipe latch 137A serializes a plurality of seventh compressed data GIO_OT6<0:7> or a plurality of eighth compressed data GIO_OT7<0:7> outputted from any one between the seventh compression block 127 and the eighth compression block 128 to output a fourth serial data DOUT<3>. The first to fourth output circuits 131B, 133B, 135B and 137B output the first to fourth serial data DOUT<0:3> as the first to fourth read data DATA_DRV<0:3> to the first to fourth pads DQ0 to DQ3 in response to the read enable signal DRV_EN.
Subsequently, a write path of the conventional semiconductor memory device is described with reference to FIGS. 2 and 3.
FIG. 2 is a block diagram illustrating a write path of the conventional semiconductor memory device, and FIG. 3 is a schematic illustrating the inside of a write circuit shown in FIG. 2.
Referring to FIG. 2, the write path of the conventional semiconductor memory device includes first to the fourth pads DQ0 to DQ3 for receiving first to fourth write data DIN<0:3> from outside of the semiconductor memory device; and a write circuit 140 for generating first to 64th array data GIO_OT<0:63> in response to data strobe signals DQS and DQSB, a write enable signal GIO_EN, and the first to fourth write data DIN<0:3> that are transferred through the first to fourth pads DQ0 to DQ3. Herein, the first to 64th array data GIO_OT<0:63> are transferred through global input/output lines. The global input/output lines correspond to the second global input/output lines through which the first to eighth compressed data GIO_OT#<0:7> are transferred.
Meanwhile, the write circuit 140 includes first to fourth data array blocks 141, 143, 145 and 147. The first to fourth data array blocks 141 to 147 arrange the first to fourth write data DIN<0:3> corresponding thereto and load the data on 16 global input/output lines corresponding thereto among the 64 global input/output lines in response to the data strobe signals DQS and DQSB and the write enable signal GIO_EN.
For example, the first data array block 141 arranges the first write data DIN<0> and outputs 16 first array data GIO_OT#<0> and GIO_OT#<4> in response to the data strobe signals DQS and DQSB and the write enable signal GIO_EN. In detail, referring to FIG. 3, the first data array block 141 comprises first to eighth data array units 141A_1, 141A_3, 141A_5, 141A_7, 141B_1, 141B_3, 141B_5 and 141B_7. The first data array unit 141A_1 outputs respective array data GIO_OT6<0> and GIO_OT6<4> and a respective latched data strobe signal DQS_LAT<0> based on the first write data DIN<0>, the data strobe signals DQS and DQSB, and the write enable signal GIO_EN. The second data array unit 141A_3 outputs respective array data GIO_OT4<0> and GIO_OT4<4> and a respective latched data strobe signal DQS_LAT<1> based on the latched data strobe signal DQS_LAT<0>, the data strobe signals DQS and DQSB, and the write enable signal GIO_EN. The third data array unit 141A_5 outputs respective array data GIO_OT2<0> and GIO_OT2<4> and a respective latched data strobe signal DQS_LAT<2> based on the latched data strobe signal DQS_LAT<1>, the data strobe signals DQS and DQSB, and the write enable signal GIO_EN. The fourth data array unit 141A_7 outputs respective array data GIO_OT0<0> and GIO_OT0<4> based on the latched data strobe signal DQS_LAT<2>, the data strobe signals DQS and DQSB, and the write enable signal GIO_EN. Likewise, the fifth to eighth data array units 141B_1 to 141B_7 outputs respective array data GIO_OT#<0> and GIO_OT#<4> based on the data strobe signals DQS and DQSB, and the write enable signal GIO_EN, and the first write data DIN<0> or respective latched data strobe signals DQSB_LAT<0:2>.
Of course, although not illustrated in the drawing, the second data array block 143 arranges the second write data DIN<1> and outputs 16 second array data GIO_OT#<1> and GIO_OT#<5> in response to the data strobe signals DQS and DQSB and the write enable signal GIO_EN. Also, the third data array block 145 arranges the third write data DIN<2> and outputs 16 third array data GIO_OT#<2> and GIO_OT#<6> in response to the data strobe signals DQS and DQSB and the write enable signal GIO_EN. The fourth data array block 147 arranges the fourth write data DIN<3> and outputs 16 fourth array data GIO_OT#<3> and GIO_OT#<7> in response to the data strobe signals DQS and DQSB and the write enable signal GIO_EN. As a result, the 64 array data GIO_OT#<0:7> are outputted as the first to 64th array data GIO—<0:63>.
Hereafter, the operation of the semiconductor memory device having the above structure is described.
In this specification, the operation is described in the order of a write operation followed by a read operation.
First, the write operation of the semiconductor memory device is described.
When the first to fourth write data DIN<0:3> are applied through the first to fourth pads DQ0 to DQ3 according to the write operation, the first to fourth data ay blocks 141 to 147 arrange the first to fourth write data DIN<0:3> in response to the data strobe signals DQS and DQSB, drive 64 total global input/output lines (16 each) in response to the write enable signal GIO_EN and load the first to 64th array data GIO—<0:63> on the 64 global input/output lines.
The first to 64th array data GIO—<0:63> loaded on the 64 global input/output lines are written in the first to eighth banks 111 to 118.
Hereafter, the read operation of the semiconductor memory device is described.
First, when the first bank 111, the second bank 113, the third bank 115, and the fourth bank 117 are activated according to the read operation, the first bank data TGIO0<0:127>, the second bank data TGIO1<0:127>, the third bank data TGIO2<0:127>, and the fourth bank data TGIO3<0:127> are output. Then, the first compression block 121, the third compression block 123, the fifth compression block 125, and the seventh compression block 127 compress the first bank data TGIO0<0:127>, the second bank data TGIO1<0:127>, the third bank data TGIO2<0:127>, and the fourth bank data TGIO3<0:127>, and output the first compressed data GIO_OT0<0:7>, the third compressed data GIO_OT2<0:7>, the fifth compressed data GIO_OT4<0:7>, the seventh compressed data GIO_OT6<0:7>, respectively.
Next, the first to fourth pipe latches 131A, 133A, 135A and 137A serialize the first compressed data GIO_OT0<0:7>, the third compressed data GIO_OT2<0:7>, the fifth compressed data GIO_OT4<0:7>, and the seventh compressed data GIO_OT6<0:7>, and output the first to fourth serial data DOUT<0:3>.
The first to fourth output circuits 131B, 133B, 135B and 137B output the first to fourth serial data DOUT<0:3> as the first to fourth read data DATA_DRV<0:3> to the first to fourth pads DQ0 to DQ3 in response to the read enable signal DR_LEN.
Accordingly, a pass/failure decision is nude for the first bank 111, the second bank 113, the third bank 115, and the fourth bank 117 based on the first to fourth read data DATA_DRV<0:3> outputted through the first to fourth pads DQ0 to DQ3.
Subsequently, when the fifth bank 112, the sixth bank 114, the seventh bank 116, and the eighth bank 118 are activated, the fifth bank data TGIO4—<0:127>, the sixth bank data TGIO5—<0:127>, the seventh bank data TGIO6—<0:127>, and the eighth bank data TGIO7—<0:127> are output. Then, the second compression block 122, the fourth compression block 124, the sixth compression block 126, and the eighth compression block 128 compress the fifth bank data TGIO4—<0:127>, the sixth bank data TGIO5—<0:127>, the seventh bank data TGIO6—<0:127>, and the eighth bank data TGIO7—<0:127>, and output the second compressed data GIO_OT1<0:7>, the fourth compressed data GIO_OT3<0:7>, the sixth compressed data GIO_OT5<0:7>, and the eighth compressed data GIO_OT7<0:7>, respectively.
Next, the first to fourth pipe latches 131A, 133A, 135A and 137A serialize the second compressed data GIO_OT1<0:7>, the fourth compressed data GIO_OT3<0:7>, the sixth compressed data GIO_OT5<0:7>, and the eighth compressed data GIO_OT7<0:7>, and output the first to fourth serial data DOUT<0:3>.
The first to fourth output circuits 131B, 133B, 135B and 137B output the first to fourth serial data DOUT<0:3> as the first to fourth read data DATA_DRV<0:3> to the first to fourth pads DQ0 to DQ3 in response to the read enable signal DRV_EN.
Accordingly, a pass/failure decision is made for the fifth bank 112, the sixth bank 114, the seventh bank 116, and the eighth bank 118 based on the first to fourth read data DATA_DRV<0:3> outputted through the first to fourth pads DQ0 to DQ3.
Since the conventional semiconductor memory device having the above structure simultaneously activates many banks at once and performs write/read operations onto data, the test time may be shortened.
The conventional semiconductor memory device having the above structure has the following drawbacks.
As mentioned above, the first to fourth pads DQ0 to DQ3 are used during the parallel test of the X4 mode. Compared with a case where a test operation is performed for each memory cell, the parallel test operation certainly reduces the test time. However, there is limitation in shortening the test time when a parallel test is performed onto a plurality of semiconductor memory devices all at once.